Finite State Machine Datapath Design, Optimization, and by Justin Davis
By Justin Davis
Finite kingdom laptop Datapath layout, Optimization, and Implementation explores the layout area of mixed FSM/Datapath implementations. The lecture begins through reading functionality matters in electronic platforms comparable to clock skew and its impact on setup and carry time constraints, and using pipelining for expanding approach clock frequency. this can be by means of definitions for latency and throughput, with linked source tradeoffs explored intimately by using dataflow graphs and scheduling tables utilized to examples taken from electronic sign processing functions. additionally, layout concerns with regards to performance, interfacing, and function for various kinds of thoughts in most cases present in ASICs and FPGAs comparable to FIFOs, single-ports, and dual-ports are tested. chosen layout examples are awarded in implementation-neutral Verilog code and block diagrams, with linked layout records on hand as downloads for either Altera Quartus and Xilinx Virtex FPGA structures. A operating wisdom of Verilog, good judgment synthesis, and easy electronic layout thoughts is needed. This lecture is appropriate as a better half to the synthesis lecture titled advent to common sense Synthesis utilizing Verilog HDL.
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Extra info for Finite State Machine Datapath Design, Optimization, and Implementation
Example text
5 shows the scheduling table for the blend implementation with the pipelined multiplier. The table entries for the bmultpipe units show two calculations, one for each pipeline stage of the bmultpipe unit. 4 schedule. ” Each clock cycle of latency is one more clock cycle that it takes for the pipeline to become full and for all execution units to become active. A pipelined datapath with a large latency is efficient as long as it has a continuous stream of input data. 11: Blend equation implementation with pipelined multiplier, latency = 3.
However, lowering the initiation period (increasing the throughput) does not affect the latency of the datapath. The cycle timing and scheduling table for an initiation period of one clock cycle are shown in Fig. 4, respectively. Observe that each resource is now utilized 100%, which is the best that can be achieved. 6, we observed that the tR2R paths of Fig. 7 were not evenly balanced, which is undesirable as the longest tR2R path determines the clock period. The excess time in the clock period for the shorter tR2R paths is wasted time; distributing the delays more evenly would produce a shorter clock period.
This delay is 11 ns. Two register-to-register delays exist for this circuit. The first is through the U1 clock-tooutput to either input on U2. The third is through the U2 clock-to-output to the input of Y on U1. Both paths have the same delay of 11+ 4 = 15 ns. 18) The three worst-case paths and the chip minimum clock period limit the clock frequency for the board-level system. The largest of these four values (0 ns, 11 ns, 15 ns, 25 ns) is 25 ns, which is also the minimum clock period for the chip.