Ultra-Low Voltage Nano-Scale Memories (Integrated Circuits by Masashi Horiguchi, Kiyoo Itoh, Hitoshi Tanaka
By Masashi Horiguchi, Kiyoo Itoh, Hitoshi Tanaka
Ultra-low voltage large-scale built-in circuits (LSIs) in nano-scale applied sciences are wanted either to fulfill the wishes of a quickly becoming cellular cellphone industry and to offset an important bring up within the strength dissipation of top-end microprocessor devices. The aim of this booklet is to supply a close rationalization of the state of the art nanometer and sub-1-V reminiscence LSIs which are taking part in decisive roles in strength unsleeping structures. rising difficulties among the machine, circuit, and approach degrees are systematically mentioned by way of trustworthy high-speed operations of reminiscence cells and peripheral good judgment circuits. The effectiveness of suggestions at equipment and circuit degrees can be defined at size via clarifying noise parts in an array, or even crucial alterations in ultra-low voltage operations among DRAMs and SRAMs.
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Extra resources for Ultra-Low Voltage Nano-Scale Memories (Integrated Circuits and Systems)
Sample text
Flash memory needs multiple power supplies internally, calling for on-chip voltage converters. A voltage down-converter, which converts the high external supply voltage to a low internal supply voltage, enables driving an internal load with a large output current. On the other hand, a voltage up-converter, by means of charge pumps, suffers from a small output current, as discussed in Chapter 8. Thus, to achieve a single external supply, the current flowing into the drain terminal at a voltage of 6 V that is generated by a pump circuit is limited to a small avalanche-breakdown current by reducing the number of cells (for example, 16 cells) that are written simultaneously.
First, equations based on KCL (Kirchhoff’s current law) are set up at the nodes of v1 vout , and vC as follows. 33) Here, gdsl << gml is assumed. From Eq. 32. Differential amplifier; circuit diagram (a), and small-signal equivalent circuit (b), where gmd is the transconductance of M1 and M2 gml is that of M3 and M4 gdsd is the drain conductance of M1 and M2 , and gdsl is that of M3 and M4 . 6. 33 shows trends in memory cell size for various memories [1] which have been presented at major conferences.
41 shows an SRAM array using the 6-T cell that consists of transfer MOSTs, M5 and M6 , driver MOSTs, M1 and M2 , and load MOSTs, M3 and M4 . The 6-T cell has offered a wide voltage margin and noise immunity and ease of fabrication with a process compatible with CMOS logic in MPUs (microprocessors). Although a cache SRAM does not need a density as high as that of a DRAM, the memory cell size is still a prime concern to reduce the fabrication cost, especially for MPUs that have a denser on-chip cache.