Power RF Circuit Design in Standard CMOS Technology by Unai Alvarado
By Unai Alvarado
Low energy intake is likely one of the severe concerns within the functionality of small battery-powered hand-held units. cellular terminals function an ever expanding variety of instant verbal exchange choices together with GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. since the whole energy to be had for every terminal is proscribed via the really gradual elevate in battery functionality anticipated within the close to destiny, the necessity for effective circuits is now critical.
This booklet provides the fundamental options to be had to layout low strength RF CMOS analogue circuits. It provides circuit designers an entire consultant of possible choices to optimize energy intake and explains the appliance of those principles within the most typical RF construction blocks: LNA, mixers and PLLs. it truly is set out utilizing useful examples and provides a distinct viewpoint because it goals designers operating in the general CMOS procedure and the entire barriers inherent in those applied sciences.
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Extra info for Power RF Circuit Design in Standard CMOS Technology
Example text
This is done through operations with the down converted quadrature components of the signal, and performs an extremely sharp selectivity. References 39 Fig. 13 Low IF architecture block diagram The digital conception of the filter plays an important role in the multi standardization of the recent front ends. It would be easy to reconfigure it in case of variation of the unwanted frequency band, or change it as can do the wanted frequency bandwidth. Furthermore, this configuration has been presented as a useful tool in the MIMO receivers (Rafati and Razavi 2007).
3 V process) and a saturation voltage (VDS,sat) of approximately 200 mV, the allowed signal swing is limited to at most 100 mV, under the assumption that the input signal is limited by the supply voltage. Hence, the threshold voltage is a strong limitation for the signal swing and, unfortunately, does not scale down at the same rate of the MOS channel length. However, further threshold voltage variation techniques might be applied in order to reduce the power consumption in CMOS circuits (see chapter 4).
A first obvious problem is the increased switch resistivity due to the reduced turn-on voltage available. To compensate this effect, transistors must be designed with larger dimensions, what leads to a larger clock feed-through and increased static power dissipation. A non-conducting region centered around VDD/2 is exhibited by complementary switch when the voltage supply is below a critical voltage Vcritical given by (Enz and Vittoz 1997): Vcritical = 2Vt 2−n Eq. 17 where n is the slope factor of the gate voltage versus pinch-off voltage.