Low Power Networks-on-Chip by Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Shekhar
By Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Shekhar Y. Borkar (auth.), Cristina Silvano, Marcello Lajolo, Gianluca Palermo (eds.)
Low energy Networks-on-Chip Edited through: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo lately, either Networks-on-Chip, as an architectural answer for high-speed interconnect, and tool intake, as a key layout constraint, have endured to realize curiosity within the layout and examine groups, considering strength and effort matters nonetheless characterize one of many proscribing elements in integrating multi- and many-cores on a unmarried chip. This booklet covers energy and effort acutely aware layout recommendations from numerous views and abstraction degrees and provides a single-source connection with one of the most very important layout thoughts proposed within the context of low-power layout for networks-on-chip architectures. •Describes an important layout options that have been invented, proposed, and utilized to lessen either dynamic energy and static strength dissipation in networks-on-chip established architectures; •Applies state of the art, low-power layout thoughts to the layout of Networks-on-Chip, to illustrate method for layout of high-speed, low-power interconnect; •Offers a unmarried resource connection with the newest learn, differently to be had merely in disparate journals and convention proceedings.
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Geyser-1: A MIPS R3000 CPU Core with Fine Grain Runtime Power Gating. In: Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC’09) (2009) 10. : A 4500 MIPS/W, 86 A Resume-Standby, 11 A Ultra-Standby Application Processor for 3G Cellular Phones. IEICE Transactions on Electronics E88-C(4), 528–535 (2005) 11. : Hierarchical Power Distribution with 20 Power Domains in 90-nm LowPower Multi-CPU Processor. In: Proceedings of the International Solid-State Circuits Conference (ISSCC’06), pp.
1 Power Domain Partitioning Before partitioning the on-chip router into a number of micro-power domains, we should estimate the gate count of each router component, since the leakage power is proportional to the device area. The RTL model of the router designed in Sect. 1 is used. As mentioned before, the router has five input physical channels, each of which has four virtual channels. Each virtual channel has a four-flit buffer queue. The flit width is 128-bit. 1 shows the gate count of each router component, such as VC buffer, output latch, CBMUX, and VCMUX (Fig.
As a target NoC, here we assume a NoC used in a chip multiprocessor illustrated in Fig. 10. Details about the chip multiprocessor will be described in Sect. 6. 6 shows the execution cycles of ten application programs selected from SPLASH-2 benchmark: (a) radix, (b) lu, (c) fft, (d) barnes, (e) ocean, (f ) raytrace, (g) volrend, (h) water-nsquared, (i) water-spatial, and ( j) fmm. As wakeup latencies, two, three, and four cycles are simulated. , no wakeup latency). As shown in Fig. 3% when the wakeup latency is two, three, and four cycles, respectively.