Hardware specification for Rocket-IO Serial Link.Rev1.4

Hardware specification for Rocket-IO Serial Link.Rev1.4

Read Online or Download Hardware specification for Rocket-IO Serial Link.Rev1.4 PDF

Best technique books

Trends in communication technologies and engineering science

Developments in communique applied sciences and Engineering technological know-how comprises revised and prolonged learn articles written by way of well-known researchers engaging in a wide overseas convention on Advances in communique applied sciences and Engineering technological know-how. The convention is held in Hong Kong, March 19-21, 2008.

The Fundamentals of Piping Design: Drafting and Design Methods for Process Applications

Written for the piper and engineer within the box, this quantity fills a big void in piping literature because the ''Rip Weaver'' books of the 90s have been taken out of print. Focussing not just on automobile CAD, but additionally on different computer-aided layout programmes to boot and handbook recommendations now not discovered wherever else, the ebook covers the complete spectrum of wishes for the piping engineer.

Penetrating Trauma: A Practical Guide on Operative Technique and Peri-Operative Management

Surgical procedure wishes ability. ability wishes wisdom. wisdom of methods, strikes, and instruments. This ebook is set such wisdom. professional authors have contributed technical pearls, won by way of years of expertise. the quick “how-I-do-it” chapters supply the reader a short and potent consultant that may be precious whilst addressing any penetrating harm.

Extra resources for Hardware specification for Rocket-IO Serial Link.Rev1.4

Sample text

For more detailed information refer to the Xilinx documentation listed at the start of this document. TX+ TXDATA CONTROL User Logic TX PCS TX PMA PCS PMA RX PCS RX PMA TX- RX+ RXDATA RX- Embedded RocketIO TRANSCEIVER VIRTEX-II PRO Figure 17: Basic transceiver model The PMA contains the serializer/deserializer (SERDES), TX and RX buffers, clock generator, and clock recovery circuitry. The PCS contains the 8B/10B encoder/decoder and the elastic buffer supporting channel bonding and clock correction.

Document No. 2. Local data element Logic generates read and write pointers and levels. It can be made of block of RAM or distributed logic, and support independent input and out put clocks or not. 3. Error handling No error handling is implemented. 6. Clocking scheme The basis of the clocking scheme is that the reference clock has to be provided directly from the input pad whereas the user clock can be buffered and match lane frequency / 20. The Xilinx Rocket IO transceiver User guide section “clocking” in chapter 3 (page 41) provides information regarding the reference clock, nevertheless, Sundance RSL standard follows the following guidelines.

8. RSL Type B, Bottom, 4 Links, TIM Pin No Pin Name Signal Description Pin No Pin Name Signal Description 1 mRxLink0p Module Receive Link 0, positive 2 mTxLink0p Module Transmit Link 0, positive 3 mRxLink0n Module Receive Link 0, negative 4 mTxLink0n Module Transmit Link 0, negative 5 mRxLink1p Module Receive Link 1, positive 6 mTxLink1p Module Transmit Link 1, positive 7 mRxLink1n Module Receive Link 1, negative 8 mTxLink1n Module Transmit Link 1, negative 9 Reserved Reserved 10 Reserved Reserved 11 Reserved Reserved 12 Reserved Reserved 13 Reserved Reserved 14 Reserved Reserved 15 Reserved Reserved 16 Reserved Reserved 17 Reserved Reserved 18 Reserved Reserved 19 Reserved Reserved 20 Reserved Reserved 21 Reserved Reserved 22 Reserved Reserved 23 Reserved Reserved 24 Reserved Reserved 25 Reserved Reserved 26 Reserved Reserved 27 Reserved Reserved 28 Reserved Reserved Document No.

Download PDF sample

Rated 4.59 of 5 – based on 23 votes
Comments are closed.