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The timing diagram of the RMW operation in the frame buffer is depicted in Fig. 20. ” In this case, the PCG sequence could be skipped in consecutive RMW operations. J. Yoo and D. Kim Fig. 20 Frame buffer access with read–modify–write scheme operation. With single-cycle RMW operation, the processor does not need to use over-clocked frequency, and memory control is simple. 3 Combination of Processing Units and Memory – Visual Image Processing Memory The other memory design technique for low-power consumption is to embed the processing units inside the memory.

Finally, Awin and Bwin, which represent the comparison results, are kept until the end of the cycle irrespective of B line voltage as shown in box (4). The 32-bit data comparator is composed of four parallel 8-bit BCLs. The 32-bit comparison results can be obtained from the four results of the four parallel BCLs by setting higher priority to the result of the MSB part BCL. As a result, the 32-bit 2-input comparator with BCL uses only 482 transistors, which are 38% less than the transistor count of the comparator reported in [31].

13(d)). From the operation of communication buffer management, efficient 1-to-N shared data transaction is clearly visible. Compared with the 1-to-1 shared data transaction, the required overhead is only sending additional (N–1) CFG packets at the start/end of the shared data transaction without making additional copy of shared data. In addition, an M-to-1 data transaction is also easily achieved by the consumer PE simply reading M VIP memories assigned to M producer PEs. The previous paragraphs dealt with how the memory-centric NoC manages the utilization of VIP memories.