Area Array Interconnection Handbook by Paul A. Totta (auth.), Karl J. Puttlitz, Paul A. Totta

Area Array Interconnection Handbook by Paul A. Totta (auth.), Karl J. Puttlitz, Paul A. Totta

By Paul A. Totta (auth.), Karl J. Puttlitz, Paul A. Totta (eds.)

Microelectronic packaging has been well-known as an enormous "enabler" for the cast­ country revolution in electronics which we now have witnessed within the final 3rd of the 20 th century. Packaging has supplied the required exterior wiring and interconnection power for transistors and built-in circuits whereas they've got undergone their very own brilliant revolution from discrete machine to gigascale integration. At IBM we're proud to have created the preliminary, easy suggestion of turn chip with solder bump connections at a time whilst a greater method was once had to improve the reliability and increase the manufacturability of semiconductors. the fundamental layout which was once selected for SLT (Solid good judgment expertise) within the Sixties was once simply prolonged to built-in circuits within the '70s and VLSI within the '80s and '90s. 3 I/O bumps have grown to 3000 with much more expected for the longer term. The package deal households have advanced from thick-film (SLT) to thin-film (metallized ceramic) to co-fired multi-layer ceramic. A later relatives or ceramics with matching expansivity to sili­ con and copper inner wiring used to be built as a predecessor of the chip interconnection revolution in copper, multilevel, submicron wiring. robust server applications were de­ veloped during which the mixed chip and package deal copper wiring exceeds a kilometer. All of this used to be completed with the consistent aim of minimizing circuit delays via brief, effective interconnects.

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Module-level test methods and strategies are described in Chapter 11. Interconnection reliability is an important issue. Various factors specifically related to flip-chip, solder-joint wear out are discussed in detail: first the methods and enhancements provided by underfilling (Chapter 12), then a detailed explanation of the major, potential reliability detractors (Chapter 13). b) Package-level Technology Section Chapters 14 through 23 discusses area-array concepts as they relate to various package form factors.

By the mid-nineties, SEMATECH and SIA had declared that a "paradigm shift" to this technology was imminent. The editors therefore agreed it would be timely and appropriate to document and extend the current knowledge about flip chip and area array packaging, and to assemble that information from a broad spectrum of knowledgeable practitioners. Purpose The electronics industry is changing rapidly. There is a broad emphasis on making products smaller, lighter, faster, cheaper, as well as more user-friendly with increased function.

Portions of key technology features, although described in detail at appropriate points in the book, are intentionally repeated in other parts when they have special relevance to the matter under discussion, or when a unique aspect was not previously discussed. Repetition is a matter of convenience, not requiring the reader to be interrupted in seeking information at other locations within the book. However, since the book is well cross-referenced, the reader has the option to collect complete, detailed information in all the referenced sections, if desired.

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