Analog-Baseband Architectures And Circuits For Multistandard by Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins

Analog-Baseband Architectures And Circuits For Multistandard by Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins

By Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins

With the earlier few decade efforts on lithography and integrated-circuit (IC) applied sciences, very reasonably cheap microsystems were effectively built for lots of assorted purposes. the rage in instant communications is towards making a networkubiquitous period within the years yet to come. Many exceptional possibilities and demanding situations, akin to layout for multi-standardability and low-voltage (LV) compliance, are quickly turning into the mainstream instructions in wireless-IC study and improvement, on condition that the previous can provide the easiest connectivity between varied networks, whereas the latter can facilitate the know-how migration into the sub-1-V nanoscale regimes for additional rate and gear aid.

Analog-Baseband Architecturees and Circuits presents architectural and circuit thoughts for instant transceivers to accomplish multistandard and low-voltage compliance. the 1st a part of the e-book studies the actual layer requisites of contemporary instant verbal exchange criteria, offers the basic tradeoffs excited by transceiver structure choice, and gives case experiences of the state of the art multistandard transceivers, the place the most important concepts strengthened are highlighted and mentioned. A statistical precis (with a hundred+ references brought up) of so much used transmitter and receiver architectures for contemporary verbal exchange criteria is equipped. all of the references are citied from the top boards, i.e., ISSCC, CICC, VLSI and ESSCIRC, from 1997 to 2005.

The moment half specializes in the architectural layout of multistandard transceivers. A coarse-RF fine-IF (two-step) channelselection procedure is disclosed. It, during the reconfiguration of receiver and transmitter analog basebands, allows not just a rest of the RF frequency synthesizer’s and native oscillator’s layout requisites, but additionally an effective multistandard compliance through synthesizing the low-IF and zero-IF within the receiver; and the direct-up and two-step-up within the transmitter. the main is established in few layout examples. considered one of them is a system-in-a-package (SiP) receiver analog baseband for IEEE 802.11a/b/g WLAN. It not just has the two-step channel choice embedded, but in addition encompasses a flexible-IF topology, a distinct 3D-stack floorplan, and a selected layout method for top testability and routability.

The 3rd half bargains with the circuit layout. as well as the methodical description of many LV circuit recommendations, three tailormade LV-robust practical blocks are provided. They contain: 1) a double-quadrature-downconversion filter out (DQDF) – it realizes at the same time clock-rate-defined IF reception, I/Q demodulation, IF channel choice and baseband filtering. 2) A switched-current-resistor (SCR) programmable-gain amplifier (PGA) – it bargains a transient-free constant-bandwidth achieve adjustment. three) An inside-OpAmp dc-offset canceler – it saves the silicon zone required for understanding a wide time consistent on chip whereas maximizing its highpass-pole switchability for speedy dc-offset transient.

The final half offers experimental result of the three tailored development blocks and a fully-integrated analog-baseband IC fabricated in a standard-VTH CMOS strategy. formerly untold on-/off-chip co-setup for either full-chip and development blocks measurements are defined. not just the construction blocks have effectively prolonged the state of the art boundary by way of sign bandwidth and provide voltage, the analog-baseband IC has been to this point the lowest-voltage-reported answer for IEEE 802.11a/b/g WLAN receivers.

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